The digital processing of images has rapidly progressed in recent years. In particular, various systems of efficient coding for compressing image data have been proposed as standards. Such efficient coding technology is used to encode image data with a reduced bit rate for improving of digital transmission, recording, etc. The CCITT (Comite Consulatif International Telegraphique et Telephoonique, or International Committee for Telephone and Telegraph) has issued: 1) Recommendation H. 261 entitled Video Coding Standard for Video-Conference and Video-Phone, 2) a JPEG (Joint Photographic Experts Group) system for encoding color still pictures and 3) an MPEG (Moving Picture Experts Group) system for encoding moving pictures (see "Unification of Efficient Encoding Systems for Images" in "Nikkei Electronics," Oct. 15, 1990, No. 511, pp. 124-129). All of these three proposals are systems principally based on a discrete cosine transform (DCT) operation.
Shown in FIG. 1 is a block diagram of a conventional efficient coding signal processor using such a DCT operation.
A luminance signal Y and two color difference signals Cr and Cb of digital image data are processed separately from each other. The luminance signal Y is transmitted in a field sequence to an input terminal 1 and stored into a field memory 2. On the other hand, the color difference signals Cr and Cb are input acrosss two input terminals 1r and 1b and are stored into a field memory 2c after multiplexed by a multiplexer 13. As the color difference signals Cr and Cb are processed after the multiplexer 13 in the same manner as the luminance signal Y, only the processing of the luminance signal Y will be representatively described hereinafter.
After conversion into a frame construction at the field memory 2, the luminance signal Y is applied to a DCT circuit 3 in blocks of 8.times.8 pixels, i.e, a square block of 8 pixels in the horizontal direction by 8 pixels in the vertical direction. The DCT circuit 3 generates DCT coefficients by an orthogonal transform of its input signals according to an 8.times.8 two-dimensional DCT. These DCT coefficients are arranged in a sequence beginning from horizontal and vertical low frequency components to their high frequency components to yield a DC coefficient representing an average of all data and sixty-three pieces of AC coefficients. The DCT coefficients are read sequentially from the horizontal and vertical low frequency components by a zigzag scan and then supplied to a quantizer 5 through a frame memory 4. The quantizer 5 reduces an amount of data (amount of data or the number of bits) by dividing the DCT coefficients read through the zigzag scan by quantization coefficients read from a quantizing table 10. Thus, the redundancy of each block signal is reduced.
Further, the quantized data are applied to a variable length encoder 6 to be encoded into, for instance, Huffman codes, based on a result calculated from a statistic amount of a quantized output. As a result, data having a high possibility of occurrence are allocated with a short length of bits, while data having a low possibility of occurrence are allocated with a long length of bits. In this manner the amount of transmission data is further reduced.
When encoded as Huffman codes, image data compressed into an amount for one sheet are made variable due to changes of image patterns. Therefore, data management in a recording operation for a prescribed recording medium is extremely inconvenient as it is unable to determine an amount of original recordable data prior to their recording operation. For this reason, a code amount allocator 11 is provided for limiting the amount of the compressed data of every frame to be equal to or less than a prescribed desired amount of image data. In this case, to compress data without deterioration of the image quality, the quantization coefficient for each block is varied in response to the input digital image data. In other words, a coefficient "a" responsive to a definition of image (i.e., a fineness of image or a ratio of high frequency component to whole frequency components) is achieved, and then the quantization coefficient is varied by multiplying a coefficient read from the quantizing table 10 with the coefficient "a". Circuit blocks 12 and 12c which are depicted by the broken line construct each adaptive quantization and variable length encoding circuits.
Now an allocation operation of bits for fixing bit rate will be described. In a block activity calculator 7c, a block activity representing an image definition of a block unit is calculated from a sum of the absolute values of the sixty-three AC coefficients contained in each block and applied to a frame activity calculator 8 and also, to the code amount allocator 11 via a frame delay circuit 9. Similar to such a block activity of the luminance signal Y, a block activity of the color difference signals Cr and Cb are also input to the frame activity calculator 8.
The frame activity calculator 8 accumulates block activities YBact and CBact of every block for one frame period, calculates frame activities YFact and CFact and obtains a ratio of the amounts of codes of the luminance signal Y and the chrominance signal C to be allocated based on these two frame activities YFact and CFact. That is, a frame activity represents an image definition of one frame unit. Then, respective amounts of codes (i.e., an amount of data and an amount of bits) YFbit and CFbit which are able to be used for the luminance signal Y and the chrominance signal C in one frame (hereinafter refered to as allocation amount of codes) are determined. Furthermore, an average activity Aact for every block is calculated by adding the allocation amounts of codes YFbit and CFbit together and the average activity Aact is converted into the coefficient "a". This coefficient "a" is applied to the quantizing table 10 so that the quantization coefficient is changed.
The block activity YBact from the block activity calculator 7 is delayed for a timing adjustment in the frame delay circuit 9 for a time corresponding to the frame activity YFact calculation and the bit allocation calculation and input to the code amount al locator 11. The allocation amounts of codes YFbit and the frame activity YFact are also input to the code amount allocator 11 so that the code amount allocator 11 calculates an allocation amount of codes YBbit which is able to be used for every block in accordance with the following equation (1) based on the block activity YBact, the allocation amount of codes YFbit and the frame activity YFact. EQU YBbit=YFbit.times.YBact/YFact (1)
As accumulation sums of the code allocation amount YBbit and the frame activity YBact in every frame are equal to the code allocation amount YFbit and the frame activity YFact, respectively, it becomes possible to suppress a predetermined amount of codes for every frame unit in this system. When the quantized output from the quantizer 5 is applied to the variable length encoder 6 and then encoded into a variable length code, the allocation amount of codes is assumed to be n2 bits. If an actual amount of codes is equal to n1 bit, in case of n1&lt;n2, i.e., the amount of quantized output bits n1 being smaller than the n2 bits, only a data amount less than the n2 bits are output as a variable length encoding data. Further, when n1&gt;n2, quantized outputs are all output as variable length encoding data. In this way, the variable length encoder 6 includes a bit limitation processing circuit (not shown) in order perform the bit allocation operation.
As described above, in the conventional efficient coding signal processor, as shown in FIG. 1, the block activity YBact and the frame activity YFact are calculated by using the present frame and its block. Also, the amount of codes capable of being used in every block is determined by multiplying the amount of codes capable of being used in every frame by the ratio of the block activity and the frame activity from the present frame and its block (Bact/Fact). However, as a period of one frame is required for calculating the frame activity Fact, the frame memory 4 is required to give an output from the DCT circuit 3 to the quantizer 5 after delaying the output for the period of one frame. In addition, there is also a problem in that the frame delay circuit 9, for delaying the block activity for the one frame period, was required in order to perform the allocation operation in the code amount allocator 11.
As described above, as the frame activity Fact was required for calculating the amount of codes to be allocated for fixing the bit rate, the conventional efficient coding signal processor had a problem in that two delay circuits are required, that is, a frame memory for delaying DCT coefficient by one frame period to determine the frame activity Fact, and another frame memory for delaying the block activity by one frame period until the allocation operation starts.